module IFID(
	clk, rst, im_dout, instr, 
	IF_PC, ID_PC, IFID_Wr, IFID_Flush, 
	PCPLUS4
);
	input clk;
	input rst;
	input [31:0] im_dout, IF_PC;
	input IFID_Wr, IFID_Flush;
	output reg [31:0] instr, ID_PC, PCPLUS4;


	always @(posedge clk, posedge rst)
	begin
		if (rst | IFID_Flush)
		begin
			instr = 0;
			ID_PC = 32'h0000_3000;
		end
		else if (IFID_Wr)
		begin
			instr = im_dout;
			ID_PC = IF_PC;
		end
	end

	always @(IF_PC)
		PCPLUS4 = IF_PC + 4;

endmodule